Intel: From Frontside to Backside Power Delivery — Intel 18A BS-PDN Technology Explained

As transistor scaling approaches fundamental physical limits, the power delivery network has emerged as a critical new bottleneck in advanced process nodes. Intel's 18A platform addresses this challenge through backside power delivery network (BS-PDN) technology, which restructures chip power architecture to achieve simultaneous improvements in performance, power consumption, and area utilization.

For years, advanced process discussions centered on EUV lithography, gate-all-around transistors, and the race toward 2-nanometer nodes. However, power delivery has become an increasingly formidable obstacle. As transistor density rises, conventional frontside power delivery networks (FS-PDN) create persistent problems including IR drop, routing congestion, power loss, and clock distribution difficulties that erode the performance gains transistors deliver.

Backside power delivery resolves these issues by relocating the power network from the front side of the wafer to the back. This separation enables genuine layered management of power and signal routing, freeing valuable interconnect resources while opening new pathways for performance enhancement, power optimization, and area reduction. As a core innovation within Intel's 18A platform, BS-PDN represents a fundamental architectural shift rather than merely an incremental process improvement.

Intel reports that BS-PDN achieves a 10x reduction in IR drop and performance gains exceeding 18%, signaling that advanced process competition is moving from the transistor era into the system architecture era.