Pennsylvania State University: Embedded Silicon Chip Capacitors in Glass Package for Vertical Power Delivery

Pennsylvania State University researchers are advancing a new power delivery architecture that combines glass substrates, through-glass vias (TGV), and embedded silicon chip capacitors to enable vertical power delivery (VPD) for next-generation AI accelerators. As the AI computing race intensifies and GPU power consumption continues climbing, advanced packaging challenges have shifted beyond compute density and bandwidth toward the fundamental question of efficiently delivering power to the chip.

The research highlights how integrating capacitors, inductors, and voltage regulation modules directly within the package dramatically shortens the power delivery path, reducing parasitic losses and improving transient response. Glass substrates offer superior electrical properties compared to organic alternatives, while TGV technology provides vertical interconnect pathways that connect power networks across stacked die. Embedded silicon capacitors deliver high capacitance density in minimal footprint, addressing decoupling requirements that conventional surface-mount components cannot meet.

This convergence of technologies signals a paradigm shift in how AI servers and high-performance computing platforms distribute power. Moving voltage regulation from the motherboard into the package itself enables tighter coupling between power conversion and the processor, a critical advantage as GPUs push toward unprecedented power envelopes.

The work underscores that beyond conventional Moore's Law scaling, power network innovation has emerged as a decisive battleground in the post-Moore era, with VPD positioned as a key enabler for future advanced packaging architectures.